DSP Compiler Mission Improving ILP By Software Pipelining Seminars/Workshops
Speaker: | Gang-Ryung Uh |
---|---|
Time: | 1999-11-03 11:00:00 |
Place: | Rm.1403, CS Bldg./KAIST |
Abstract
Several companies have recently introduced DSP oriented
microprocessors embodying a computer architecture design
style called VLIW (very long instruction word architecture)
to exploit ILP (instruction level parallelism) available
in DSP applications. Examples of such architecture includes
TI-C6 family, Lucent SC140 family, TriMedia DSP, and etc.
My talk will include
- Pipelining and DSPs
- ILP Hardwares and VLIW based DSPs
- Compiler missions for VLIW based DSPs
- Significance of Software Pipelining
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